Thanks to the laws of physics and Moore, there is only so much silicon we can fit in a single device. The challenge has always been to cram as many components as possible without increasing the amount of space as much as possible. In addition to improving manufacturing processes, one of the keys to that puzzle is thinking of creative ways to accomplish old techniques and designs. That is what Samsung is boasting off in its new DRAM technology that is able to stack 12 DRAM chips in the same space as 8 chips by ditching the traditional wire-bonding technique for TSV.
Silicon makers have gone three-dimensional because of space constraints. When you can’t expand horizontally, you try to expand vertically. Stacking chips is often made possible using wire-bonding but those wires, thin as they are, still take up space between layers of chips.
3D Through-Silicon Via or TSV, in contrast, passes the connector through the chips, as the name of the technology suggests. not only does it take up less space horizontally, it also reduces the padding between each layer of silicon. Additionally, it even reduces the overall materials used because the connection between chips and the PCB beneath is also shorter.
Despite the many benefits, TSV technology is actually more difficult to pull off and also more expensive. In fact, Samsung’s announcement reveals it used no less than 60,000 holes to make this happen. Just as impressive, however, is how it managed to use that technology to have 12 DRAM chips stacked in the same height as its previous 8-layer wire-bonded DRAM solutions, which is just 720㎛ (micrometers) tall.
The bottom line is that it can offer an even higher capacity DRAM product in the same space occupied by its current ones. Specifically, Samsung is planning on producing 24 GB DRAM via this 12-layer 3D TSV technology. That, however, is targeted at its High-Bandwidth Memory 2 (HBM2) line, which hints at how expensive and how rare it will be, even for enterprise customers.