NEC have developed a 32Mb MRAM chip that, thanks to the company’s efforts to miniturize the control circuits, allows 73-percent of a memory macro’s area to be allocated to memory cells. The MRAM chip, which is intended for SoC (System-on-Chip) products such as those found in embedded and mobile devices, is also compatible with asynchronous SRAM.
Meanwhile the MRAM chip’s cycle time is just 9ns, courtesy of a new set of new decoder circuits . The most significant size reduction was gained through the introduction of a word boost circuit in the macro’s word line decoder circuit; NEC had to develop a word boost circuit featuring optimized conversion levels in order to reduce delay and the tendency of word boos circuits to extend the cycle time of macros.
The company claims that their next challenge is to demonstrate a viable SoC using one or more of the MRAM chips, to prove the effectiveness of the technology. No timescale has been given for when we could see products using the new 32Mb chip.