Not too long ago, Samsung and Qualcomm boasted their Exynos 8895 and Snapdragon 835 processors, respectively. Both of these chips were manufactured using a 10 nm FinFET process, currently the smallest chip size in the consumer market. IBM’s Research Alliance, however, is proving that it has done one better. By halving the size but increasing performance and energy efficiency, IBM’s 5 nm chips has the potential to push the consumer electronics market forward, especially the IoT and even the smartphone markets, at an accelerated pace.
IBM makes it clear that 5 nm chips are also possible using the now standard FinFET transistor architecture, which takes its name from the fin-like silicon structure that wraps around the transistor’s conductive channel. Those fins, however, also limit how much space the transistors can safely take up. So while the FinFET process can indeed scale down to 5 nm, there are no other benefits other than the smaller size.
In contrast, IBM’s nanosheet architecture promises not only a smaller size but also a bigger performance improvement. This is made possible by using nanosheets instead of fins as the main structure of the transistors. This not only allows IBM to cram even more in a tiny space but also offers some flexibility to change the width of the nanosheets even in a single manufacturing process.
In theory, IBM Research claims that the chips offer a 40% performance boost at a fixed power. Alternatively, it offers 75% power savings when running to match the performance of a 10 nm FinFET chip. All at half the size of the chips you’ll find in something like the Samsung Galaxy S8.
More power at less space and battery drain is something that modern electronics are in great need of, from smartphones to machine learning platforms to IoT devices. Especially for the latter, which are severely limited by how much silicon can be crammed in such a small space, IBM’s 5 nm chips could give the industry the break it needs to become smarter and more capable in powering the smart homes of tomorrow.