http://www.slashgear.com/globalfoundries-apes-intel-with-3d-20nm-chips-26224886/ Feeding Your Gadget and Tech Obsessions Tue, 15 May 2012 14:06:00 +0000 hourly 1 http://wordpress.org/?v=3.5.1 http://www.slashgear.com/globalfoundries-apes-intel-with-3d-20nm-chips-26224886/#comment-210703 HarshaBharadhwaj Tue, 15 May 2012 10:07:00 +0000 http://www.slashgear.com/?p=224886#comment-210703 Author is ignorant of the technological differences and has posted this just going by 3D statements. GF is not aping Intel here. GF is up-to an altogether different dimension.

]]> http://www.slashgear.com/globalfoundries-apes-intel-with-3d-20nm-chips-26224886/#comment-205548 jcamdr Thu, 26 Apr 2012 19:46:00 +0000 http://www.slashgear.com/?p=224886#comment-205548 After the memory, stack the power supply converter into the package and this will be a ideal product. For the integrator, it will be easy to use by just connecting standard supply and standard I/O bus depending on the application. For the manufacturer, this open bigger optimization opportunity because many external interfaces will became internal and can me changer without problem for the integrator.

]]> http://www.slashgear.com/globalfoundries-apes-intel-with-3d-20nm-chips-26224886/#comment-205514 Ernie Costello Thu, 26 Apr 2012 17:47:00 +0000 http://www.slashgear.com/?p=224886#comment-205514 Ben, 
3-D stacking (like with through silicon vias, or TSVs) are vertical connections that pass through die to connect different layers of a chip within the same package. Intel’s tri-gates are actually 3-D transistors,known outside Intel as a FinFEts, are a 3D transistor technology. The two areas are different technologies. 

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