There was an interesting little nugget of information in the TSMC financial results this morning. The company was planning to develop 20nm manufacturing capabilities, but they’re not the only ones hoping to achieve that goal. GlobalFoundries has announced that it has installed specialty production tools at its New York plant capable of 3D stacking 20nm chips.
The tools help the company to create Through-Silicon Vias (TSVs), which allows customers to stack multiple chips on top of each other. The new development could allow manufacturers to stack memory chips right on top of the processor, which would drastically improve performance and lead to reduced power consumption.
3D stacking could be the next logical progression for manufacturers instead of simply scaling upwards at the transistor level. The increasing complexity of chip designs means foundries and partners could soon struggle, something which vertical stacking could help avoid. Gregg Bartlett, chief technology officer of GlobalFoundries, says its approach can deliver cost and time savings, and reduce “technical risk associated with developing new technologies.”
If 3D stacking sounds familiar, it’s because Intel employs a similar method with the transistors on the current Ivy Bridge processors. The method has helped Intel increase performance while also reducing power consumption by around 20%. It only costs around 2-3% more than traditional 2D transistors as well. 20nm development, meanwhile, is said to be underway, with the first TSVs expected to begin production in Q3 of this year.